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august 2006 rev 1 1/21 1 TDA7303 digital controlled stereo au dio processor with loudness features input multiplexer: ? 3 stereo inputs ? selectable input gain for optimal adaption to different sources volume control in 1.25db steps loudness function treble and bass control four speaker attenuators: ? 4 independent speakers control in 1.25db steps for balance and fader facilities ? independent mute function all functions programmable via serial i 2 c bus description the TDA7303 is a volume, tone (bass and treble) balance (left/right) and fader (front/rear) processor for quality audio applications in car radio, hi-fi and portable systems. selectable input gain and external loudness function are provided. control is accomplished by serial i 2 c bus microprocessor interface. the ac signal setting is obtained by resistor networks and switches combined with operational amplifiers. thanks to the used bipolar/cmos tecnology, low distortion, low noise and low dc stepping are obtained. order codes so-28 part number package packing TDA7303 so-28 tray TDA7303tr so-28 tape and reel www.st.com
contents TDA7303 2/21 contents 1 block, test & pins diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 data bytes (detailed description) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TDA7303 list of tables 3/21 list of tables table 1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. audio switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. bass and treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
list of figures TDA7303 4/21 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. loudness vs volume attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. loudness vs. frequency (cloud = 100nf) vs. volume attenuation . . . . . . . . . . . . . . . . 10 figure 6. loudness versus external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. noise versus volume/gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. signal to noise ratio vs. volume setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. distortion & noise vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 10. signal to noise ratio vs. volume setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 11. distortion vs. load resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 12. channel separation (l ? r) vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13. input separation (l1 ? l2, l3) vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 14. supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 15. output clipping level vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 16. quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 17. supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 18. bass resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 19. typical tone response (with the ext. components indicated in the test circuit). . . . . . . . . 12 figure 20. data validity on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 21. timing diagram of s-bus and i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 22. acknowledge on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 23. so-28 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TDA7303 block, test & pins diagrams 5/21 1 block, test & pins diagrams 1.1 block diagram figure 1. block diagram l1 15 l1 l2 14 l2 l3 13 l3 input selector + gain c1 c2 c3 left inputs 3x 2.2 f supply r3 9 r3 r2 10 r2 r1 11 r1 c4 c5 c6 3x 2.2 f right inputs 231 v s agnd cref c9 2.2 f out(l) in(l) 17 16 vol + loud loud(l) 12 100nf c14 bass 19 5.6k r2 bout(l) 18 bin(l) 100nf c15 rb treble c17 2.7nf treble(l) 4 mute d98au888 serial bus decoder + latches spkr att 25 vol + loud bass treble out(r) in(r) c8 2.2 f 76 100nf c12 100nf c13 5.6k r1 bout(r) bin(r) 21 20 rb 2.7nf c16 treble(r) mute spkr att 28 27 26 22 scl sda diggnd bus out right rear out left front 5 22 f c7 8 loud(r) c11 100nf 100nf c10 mute spkr att out left rear 23 mute spkr att out right front 24
block, test & pins diagrams TDA7303 6/21 1.2 test circuit figure 2. test circuit 1.3 pins connection figure 3. pin connection (top view)
TDA7303 electrical specifications 7/21 2 electrical specifications 2.1 absolute maximum ratings 2.2 quick reference data 2.3 thermal data table 1. absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.0 v t amb ambient temperature -40 to 85 c t stg storage temperature range -55 to +150 c table 2. quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 % s/n signal to noise ratio 106 db s c channel separation f = 1khz 103 db volume control 1.25db step -78.75 0 db bass and treble control 2db step -14 +14 db fader and balance contro l 1.25db step -38.75 0 db input gain 3.75db step1.25db step 0 11.25 db mute attenuation 100 db table 3. thermal data symbol parameter value unit r th j-pins thermal resistance junction-pins max 85 c/w
electrical specifications TDA7303 8/21 2.4 electrical characteristics table 4. electrical characteristcs (t amb = 25c, v s = 9v, r l = 10k ? , r g = 600 ? , all control flat (g=0), f = 1khz unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10 v i s supply current 8 11 ma svr ripple rejection 60 80 db input selectors r ii input resistance input 1, 2, 3, 4 50 k ? v cl clipping level 2 2.5 vrms s in input separation (2) 80 100 db r l output load resistance pin 7, 17 2 k ? g inmin min. input gain -1 0 1 db g inmax max. input gain 11.25 db g step step resolution 3.75 db e in input noise g = 11.25db 2 v volume control r in input resistance 33 k ? c range control range 70 75 80 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 70 75 80 db a step step resolution 0.5 1.25 1.75 db e a attenuation set error a v = 0 to -20db -1.25 0 1.25 db a v = -20 to -60db -3 2 db e t tracking error 2db speaker attenuators c range control range 35 37.5 40 db s step step resolution 0.5 1.25 1.75 db e a attenuation set error 1.5 db a mute output mute attenuation 80 100 db bass control (1) gb control range max. boost/cut 12 14 16 db b step step resolution 1 2 3 db
TDA7303 electrical specifications 9/21 r b internal feedback resistance 44 k ? treble control (1) gt control range max. boost/cut 13 14 15 db t step step resolution 1 2 3 db audio outputs v ocl clipping level d = 0.3% 2 2.5 vrms r l output load resistance 2 k ? c l output load capacitance 10 nf r out output resistance 75 w v out dc voltage level 4.2 4.5 4.8 v general e no output noise (2) bw = 20-20khz, flat output muted all gains = 0db 2.5 5 v v a curve all gains = 0db 3 v s/n signal to noise ratio all gains = 0db; v o = 1vrms 106 db d distortion a v = 0; v in = 1vrms 0.01 % a v = 20db, v in = 1vrms 0.09 0.3 % a v = 20db, v in = 1vrms 0.04 % sc channel separation left/right 80 103 db total tracking error a v = 0 to -20db 0 1 db -20 to -60 db 0 2 db bus inputs v il input low voltage 1v v ih input high voltage 3 v i in input current -5 +5 a v o output voltage sda acknowledge i o = 1.6ma 0.4 v 1. bass and treble response see attached diagram (fig.22). th e center frequency and quality of the resonance behaviour can be choosen by the external circuitry. a standard first order bass re sponse can be realized by a standard feedback network 2. the selected input is grounded thru the 2.2f capacitor. table 4. electrical characteristcs (continued) (t amb = 25c, v s = 9v, r l = 10k ? , r g = 600 ? , all control flat (g=0), f = 1khz unless otherwise specified) symbol parameter test condition min. typ. max. unit
electrical specifications TDA7303 10/21 2.5 electrical characteristics curves figure 4. loudness vs volume attenuation figure 5. loudness vs. frequency (c loud = 100nf) vs. volume attenuation figure 6. loudness versus external capacitors figure 7. noise versus volume/gain setting figure 8. signal to noise ratio vs. volume setting figure 9. distortion & noise vs. frequency
TDA7303 electrical specifications 11/21 figure 10. signal to noise ratio vs. volume setting figure 11. distortion vs. load resistance figure 12. channel separation (l r) vs. frequency figure 13. input separation (l1 l2, l3) vs. frequency figure 14. supply voltage rejection vs. frequency figure 15. output clipping level vs. supply voltag e
electrical specifications TDA7303 12/21 figure 16. quiescent current vs. supply voltag e figure 17. supply current vs. temperature figure 18. bass resistance vs. temperature f igure 19. typical tone response (with the ext. components indicated in the test circuit)
TDA7303 i2c bus interface 13/21 3 i 2 c bus interface data transmission from microprocessor to the TDA7303 and viceversa takes place thru the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). 3.1 data validity as shown in figure 20 , the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 3.2 start and stop conditions as shown in figure 21 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. 3.3 byte format every byte transferred on the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 3.4 acknowledge the master ( p) puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 22 ). the peripheral (audioprocessor) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. 3.5 transmission without acknowledge avoiding to detect the acknowledge of the audioprocessor, the p can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity.
i2c bus interface TDA7303 14/21 figure 20. data validity on the i 2 c bus figure 21. timing diagram of s-bus and i 2 c bus figure 22. acknowledge on the i 2 c bus patent note: purchase of i 2 c components of stmicrolectronics, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. sda scl data line stable, data valid change data allowed d99au1031 scl sda start i 2 cbus stop d99au1032 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033
TDA7303 software specification 15/21 4 software specification 4.1 interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the TDA7303 address (the 8th bit of the byte must be 0). the TDA7303 must always acknowledge at the end of each transmitted byte. a sequence of data (n-bytes + acknowledge) a stop condition (p) ack = acknowledge s = start p = stop max clock speed 100kbits/s 4.2 subaddress (receive mode) ax = 1.25db steps; bx = 10db steps; cx = 2db steps; gx = 3.75db steps table 5. chip address 1 msb 000100 0 lsb table 6. data bytes msb lsb function 0 0 b2 b1 b0 a2 a1 a0 volume control 1 1 0 b1b0a2a1a0speaker att lr 1 1 1 b1b0a2a1a0speaker att rr 1 0 0 b1b0a2a1a0speaker att lf 1 0 1 b1b0a2a1a0speaker att rf 0 1 0 g1 g0 s2 s1 s0 audio switch 0 1 1 0 c3 c2 c1 c0 bass control 0 1 1 1 c3 c2 c1 c0 treble control
software specification TDA7303 16/21 4.3 data bytes (detailed description) for example a volume of -45db is given by: 0 0 1 0 0 1 0 0 for example attenuation of 25db on speaker rf is given by: 1 0 1 1 0 1 0 0 table 7. volume msb lsb function 0 0 b2 b1 b0 a2 a1 a0 volume 1.25db steps 000 0 0 0 1 -1.25 010 -2.5 0 1 1 -3.75 100 -5 1 0 1 -6.25 110 -7.5 1 1 1 -8.75 0 0 b2 b1 b0 a2 a1 a0 volume 10db steps 000 0 001 -10 010 -20 011 -30 100 -40 101 -50 110 -60 111 -70 table 8. speaker attenuators msb lsb function 1 0 0 b1 b0 a2 a1 a0 speaker lf 1 0 1 b1 b0 a2 a1 a0 speaker rf 1 1 0 b1 b0 a2 a1 a0 speaker lr 1 1 1 b1 b0 a2 a1 a0 speaker rr 000 0 0 0 1 -1.25 010 -2.5 0 1 1 -3.75 100 -5 1 0 1 -6.25 110 -7.5 1 1 1 -8.75 00 0 01 -10 10 -20 11 -30 11111 mute
TDA7303 software specification 17/21 for example to select the stereo 2 inpu t with a gain of +7.5db loudness on the 8bit string is: 0 1 0 0 1 0 0 1 c3 = sign for example bass at -10db is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 table 9. audio switch msb lsb function 0 1 0 g1 g0 s2 s1 s0 audio switch 0 0 stereo 1 0 1 stereo 2 1 0 stereo 3 11 not allowed 0 loudness on 1 loudness off 0 0 +11.25db 0 1 +7.5db 10 +3.75db 1 1 0db table 10. bass and treble msb lsb function 0 1 1 0 c3c2c1c0 bass 0 1 1 1 c3c2c1c0 treble 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14
package information TDA7303 18/21 5 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 23. so-28 mechanical data & package dimensions so-28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data
TDA7303 revision history 19/21 6 revision history table 11. document revision history date revision changes 04-aug-2006 1 initial release.
TDA7303 20/21 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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